For this purpose, the metal coating structure is arranged on the active upper side of the semiconductor chip above passivation layers. This metal coating structure has copper-containing interconnects and contact terminal areas to contact areas of the semiconductor elements of the semiconductor chip. In this case, a copper-containing metal layer takes over the main load of the power supply and has correspondingly thick interconnect cross sections. These copper-containing layers of the metal tracks are used instead of the otherwise usual aluminum layer to provide a better current-carrying capacity in the case of power semiconductor technologies.
Such a copper-containing current-carrying layer of the interconnects may cover over half the active upper side of the semiconductor chip. In order to permit corrosion protection of the copper and bonding of correspondingly thick aluminum wires, this copper-containing metal area is covered by a sequence of metal layers of NiP/Pg/Au. In order to avoid diffusion of the copper into the passivation layers lying thereunder of the semiconductor chip surface, a lowermost layer of a copper-diffusion-inhibiting material, such as tungsten and/or titanium, is additionally arranged on the passivation layer of the semiconductor chip.
The special characteristic feature of such metal coatings of the semiconductor chip is that they have mirror-smooth surfaces, in order to permit a geometrically and topographically exact coating structure and to ensure reliable corrosion protection for the current-carrying copper layer. Such mirror-smooth surfaces of metal have the disadvantage of poor molding compound adhesion for a polymeric plastic package molding compound on the mirror-smooth metal-coated upper side of the chip. As a result, there is the risk of delamination between the plastic package molding compound and the mirror-smooth surface of the interconnects on the upper side of the chip. This may have the consequence that the metallization and/or the chip passivation become damaged, in particular under changing thermal loads. Moisture can enter by diffusion at the delaminated chip surfaces and may lead, inter alia, to leakage currents and even short-circuits between neighboring interconnects. Furthermore, in the case of microcracks in the passivation layer, moisture diffusion may also penetrate further into the chip and lead there to chip malfunctions.
The poor molding compound adhesion on the upper side of the chip that usually occurs with mirror-smooth aluminum metallizations can be successfully overcome, by applying a polymer layer, for example a photoimide, or by other standard measures for improving the adhesion between the chip surface and the surrounding plastic molding compound, in the case of mirror-smooth aluminum metallizations and/or precious metallizations only because the metallizations have an extremely small topology. This is so because these metallizations are usually less than 1 μm thick, so that the steps in layer thickness on the upper side of the semiconductor chip between the interconnects and the passivation layer are negligible in comparison with the thickness of the polymeric adhesion coatings.
With the extremely great topology of the copper conduction layers, with differences in height sometimes in excess of 5 μm, however, the transferability of this polymer process to improve the adhesion is problematical. The polyimide distributes itself with difficulty and not completely into all the grooves, which causes the metallization structure with such a thickness. This may have the effect when the polyimide is applied of creating voids, in which once again moisture can collect, which may lead to the aforementioned disadvantages. In addition, it would be necessary when curing the polyimide to provide special ovens for the copper-containing metallization, in order to avoid contamination of standard wafers that only have aluminum interconnects. The attempt to adapt the molding compounds in their adhesive property to the uppermost precious metal layers for example is also problematical, especially since these precious metals, such as palladium and gold, appear to be unsuitable from the outset for molding compound adhesion.
Special galvanically deposited ceramic layers, such as are known from the document DE 101 48 120.9, cannot be applied in practice at the semiconductor wafer level, in order to provide them uniformly on all chip surfaces, since these processes, though suitable for the finally mounted semiconductor chip, represent a risk of contamination for installations and equipment in the case of a semiconductor wafer.
However, there is the need to provide these metal coating surfaces with copper-containing layers, suitable for further processing, simultaneously for a number of semiconductor chips at semiconductor wafer level before the semiconductor wafer is separated into individual semiconductor chips, without performing additional process steps.